The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a capacitor.
A so-called MIM (metal-insulator-metal) capacitor is used extensively as a capacitance element in various analog circuits including A/D converters or semiconductor integrated circuits that includes a pump circuit of a flash memory.
Such an MIM capacitor is generally integrated into a multilayer interconnection structure such that the MIM capacitor constitutes a part of the multilayer interconnection structure.
FIG. 1 shows an example of a conventional MIM capacitor.
Referring to FIG. 1, the MIM capacitor is formed of a metal pattern M1 constituting a first metal layer of a multilayer interconnection structure, a metal pattern M2 opposing the metal pattern M1 across an interlayer insulation film not illustrated and constituting a second metal layer of the multilayer interconnection structure, and a metal pattern M3 opposing the metal pattern M2 across an interlayer insulation film not illustrated and constituting a third metal layer of the multilayer interconnection structure. Thereby, a capacitance C is formed above and below the metal pattern M2.
In the illustrated example, the metal pattern M1 and the metal pattern M3 are connected parallel with each other, and there is formed a capacitor having a capacitance value 2C such that the capacitor has the metal pattern M2 as a first electrode and the metal patterns M1 and M3 as the second electrode.
With the semiconductor device having such an MIM capacitor, it should be noted that the capacitor itself is miniaturized with miniaturization of the semiconductor device, and thus, there arises a problem of securing sufficient capacitance, particularly for such highly miniaturized capacitors.
In order to secure sufficient capacitance value with such an MIM capacitor integrated to the multilayer interconnection structure also for the case the area of the electrodes is reduced, it is necessary to reduce the thickness of the interlayer insulation film interposed between the metal patterns M1, M2 and M3. However, in the case the MIS capacitor is integrated to the multilayer interconnection structure, such decrease of film thickness of the interlayer insulation film inevitably leads to the problem of increased stray capacitance between the interconnection patterns formed in the multilayer interconnection structure.
Because of such situations and circumstances, it has been difficult to reduce the size of the MIM capacitor shown in FIG. 1, and there has been caused a problem at the time of designing a semiconductor integrated circuit device that uses such an MIM capacitor.
Meanwhile, there is proposed an MIM capacitor shown in FIG. 2 that uses a comb-shaped electrode formed in a multilayer interconnection structure. Reference should be made to Patent Reference 1.